Projects‎ > ‎

Gatrack

(Spring 2006, Supervisor: Prof. Aparajita Ojha new windowIIITDM Jabalpur new window)

We were learning Logic Gates in the course of Computer Architecture. For in-depth understanding of the working of Gates, I implemented a small tool for the analysis of Tracks with the Logic Gates.
  • A small tool for the analysis of Logic gates and their behavior
  • Verification of some basic laws of Boolean Algebra
  • Digital signal processing for basic operations
  • 8-bit Interactive full adder simulation
Language Used: C/C++                                                                                                            
Duration: 4 Months

Led a team of 3 members
Comments